FIG. 14 is a plan view showing a conventional semiconductor integrated circuit. FIG. 15 is a side cross sectional view taken along line E—E shown in FIG. 14. As shown in FIGS. 14 and 15, in a conventional semiconductor integrated circuit, a multilayer interconnection layer 101 can be provided on a semiconductor substrate (not shown). An inductor 103 is a spiral inductor provided on an uppermost layer 102 of the multilayer interconnection layer 101. In more detail, the inductor 103 includes one wiring arranged in a spiral, and formed on an insulating layer 104 of silicon dioxide (SiO2) that is included within multilayer interconnection layer 101. In addition, an insulating layer 105 of SiO2 can be provided to cover inductor 103. Further, an insulating layer 106 of polyimide is provided on insulating layer 105.
It is noted that insulating layers 105 and 106 are omitted from FIG. 14.
A wiring of the inductor 103 is formed with wiring main body 107 of copper or aluminum. The wiring main body 107 has an upper surface and lower surface covered with a titanium-tungsten (TiW) layer 108.
Inductor 103 is provided on an uppermost layer 102 of a multilayer interconnection layer 101 in order to reduce, as much as possible, any parasitic capacitance between the inductor 103 and semiconductor substrate. In addition, a thickness of the wiring of the inductor 103 is increased as much as possible in order to reduce a series resistance for such an inductor 103. Reducing series resistance can improve a quality factor (Q-factor) of the inductor 103.
A conventional semiconductor integrated circuit, like that of FIGS. 14 and 15, can have a number of drawbacks. First, a thickness of an uppermost layer 102 can be about 10 microns (μm). Thus, when an inductor 103 is included in an uppermost layer 102 of a multilayer interconnection layer 101, such an inductor 103 can have thickness with an upper limit of several microns. Such a limited thickness may result in loss of inductance and an undesirably small Q-factor (about 5 to 10). Second, in order to obtain an inductance of about 10 nano-Henries (nH), a conventional inductor 103 has a spiral shape (vortex) of a square with sides of 200 to 300 μm. As a result, the area of a conventional inductor 103 can be undesirable large, thus limiting the extent to which a semiconductor conductor integrated circuit can be scaled down in size.
Conventionally, ferromagnetic substance layers have been formed with inductors in particular arrangements.
A conventional technique for providing a layer of a ferromagnetic substance as an upper layer of an inductor is disclosed in Japanese Utility Model Application Publication 3-28758 (JU 3-28758). In JU 3-28758, a ferromagnetic substance layer is provided above a vortex with respect to a vertical position, and within the inner sides of the vortex, with respect to a lateral position.
Japanese Utility Model Application Publication 4-63653 (JU 4-63653) shows another conventional technique in which a ferromagnetic substance layer is provided either above or below an inductor. In JU 4-63653, a ferromagnetic substance layer is provided that covers the inductor when the inductor is viewed perpendicular to the surface of the substrate.
Japanese Patent Application Publication 61-161747 (JP 61-161747) shows another conventional technique in which a ferromagnetic substance layer is provided above an inductor. In JP 61-161747, it is noted that the inclusion of such a ferromagnetic substance layer increases the inductance of the inductor.
However, conventional approaches like those shown above can have drawbacks. In semiconductor integrated circuits with conventional inductors, such as those described in JU 3-28758, JU 4-63653 and JP 61-161747, a Q-factor for a resulting inductor may not be sufficient for certain applications. Thus, in order to arrive at a predetermined inductance, and inductor with a larger area can be required. However, such large area inductors limit the extent to which a semiconductor integrated circuit can be scaled down in size.
In light of the above-mentioned drawbacks, it would be desirable to arrive at a semiconductor integrated circuit, with an inductance and Q-factor that are acceptably high, which is also capable of being miniaturized as the same time. It would also be desirable to arrive at a method of manufacturing such a semiconductor integrated circuit.